IO-APIC interrupt delivery mode on Ryzen

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IO-APIC interrupt delivery mode on Ryzen

Andriy Gapon

A while ago I discovered that all AMD IO-APICs (in separate southbridges and in
FCHs) had a bug with respect to how the interrupt delivery mode got interpreted.
I am curious if the problem has been fixed in Ryzen or if it is being carried on.

I would appreciate any help with testing that.

The discussion of the problem and the tests I used can be found in this thread:

If you are interested and it's not really clear how to conduct a test, please
write me.

Thank you!
Andriy Gapon
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